Freescale Semiconductor /MKW21Z4 /XCVR_CTRL_REGS /PACKET_RAM_CTRL

Packet RAM Debug Page Selector

0 (0000): Packet RAM Debug Mode Idle

1 (0001): RX_DIG I and Q

4 (0100): RAW ADC I and Q

7 (0111): DC Estimator I and Q

10 (1010): RX_DIG Phase Output

11 (1011): Demodulator Hard Decision

12 (1100): Demodulator Soft Decision

13 (1101): Demodulator Data Output

14 (1110): Demodulator CFO Phase Output

Packet Buffer Protect

0 (0): Incoming received packets overwrite Packet Buffer RX contents (default)

1 (1): Incoming received packets are blocked from overwriting Packet Buffer RX contents

Allow Packet RAM Transceiver Access

0 (0): Protocol Engines, and associated IPS busses, have exclusive access to Packet RAM (mission mode)

1 (1): Transceiver-space access to Packet RAM, including Packet RAM debug mode, are allowed

Allow IPS bus access to Packet RAM for any protocol at any time.

0 (0): IPS bus access to Packet RAM is restricted to the protocol engine currently selected by XCVR_CTRL[PROTOCOL].

1 (1): All IPS bus access to Packet RAM permitted, regardless of XCVR_CTRL[PROTOCOL] setting

DBG_TRIGGERRED

DBG_RAM_FULL[1:0]

0 (00): Neither Packet RAM0 nor RAM1 is full

1 (x1): Packet RAM0 has been filled to capacity.

2 (1x): Packet RAM1 has been filled to capacity.

Override control for RAM0 Clock Gate Enable

0 (0): Normal operation.

1 (1): Use the state of RAM0_CLK_ON_OVRD to override the RAM0 Clock Gate Enable.

Override value for RAM0 Clock Gate Enable

Override control for RAM1 Clock Gate Enable

0 (0): Normal operation.

1 (1): Use the state of RAM1_CLK_ON_OVRD to override the RAM1 Clock Gate Enable.

Override value for RAM1 Clock Gate Enable

Override control for RAM0 CE (Chip Enable)

0 (0): Normal operation.

1 (1): Use the state of RAM0_CE_ON_OVRD to override the RAM0 CE.

Override value for RAM0 CE (Chip Enable)

Override control for RAM1 CE (Chip Enable)

0 (0): Normal operation.

1 (1): Use the state of RAM1_CE_ON_OVRD to override the RAM1 CE.

Override value for RAM1 CE (Chip Enable)